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author | Andreas K. Hüttel <dilfridge@gentoo.org> | 2020-09-11 22:04:38 +0300 |
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committer | Andreas K. Hüttel <dilfridge@gentoo.org> | 2020-09-11 22:04:38 +0300 |
commit | ff88ce93296fc216eded48e4b26a1354380e3d60 (patch) | |
tree | db32c2bb7771f0a55e98a08bbf2aea0c15516c2e | |
parent | Allow "interpreter" parameter as space-separated list of files (diff) | |
download | catalyst-ff88ce93296fc216eded48e4b26a1354380e3d60.tar.gz catalyst-ff88ce93296fc216eded48e4b26a1354380e3d60.tar.bz2 catalyst-ff88ce93296fc216eded48e4b26a1354380e3d60.zip |
Add rv32 subarch names (all cflags magic is done in the profiles)
Signed-off-by: Andreas K. Hüttel <dilfridge@gentoo.org>
-rw-r--r-- | catalyst/arch/riscv.py | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/catalyst/arch/riscv.py b/catalyst/arch/riscv.py index 9f7a421f..18695b51 100644 --- a/catalyst/arch/riscv.py +++ b/catalyst/arch/riscv.py @@ -28,6 +28,16 @@ class arch_rv64_lp64(generic_riscv): def __init__(self,myspec): generic_riscv.__init__(self,myspec) +class arch_rv32_ilp32d(generic_riscv): + "builder class for rv64_lp64" + def __init__(self,myspec): + generic_riscv.__init__(self,myspec) + +class arch_rv32_ilp32(generic_riscv): + "builder class for rv64_lp64" + def __init__(self,myspec): + generic_riscv.__init__(self,myspec) + def register(): "Inform main catalyst program of the contents of this plugin." @@ -35,5 +45,7 @@ def register(): "riscv" : arch_riscv, "rv64_multilib" : arch_rv64_multilib, "rv64_lp64d" : arch_rv64_lp64d, - "rv64_lp64" : arch_rv64_lp64 + "rv64_lp64" : arch_rv64_lp64, + "rv32_ilp32d" : arch_rv32_ilp32d, + "rv32_ilp32" : arch_rv32_ilp32 }, ("rv64_multilib")) |