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authorAndreas K. Hüttel <dilfridge@gentoo.org>2022-07-30 20:41:18 +0200
committerAndreas K. Hüttel <dilfridge@gentoo.org>2022-07-30 20:41:18 +0200
commit4f2fd56455090dfa618857616f3ca1afc10663e3 (patch)
tree86b919c585520c23af6c5a90e05e76991d89f1d6
parentCompile mipsel3 stages with -mfix-r5900 (diff)
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arch: Add subarch definition for riscv64 softfloat musl
Signed-off-by: Andreas K. Hüttel <dilfridge@gentoo.org>
-rw-r--r--catalyst/arch/riscv.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/catalyst/arch/riscv.py b/catalyst/arch/riscv.py
index d7b76c37..975bce99 100644
--- a/catalyst/arch/riscv.py
+++ b/catalyst/arch/riscv.py
@@ -34,6 +34,12 @@ class arch_rv64_lp64(generic_riscv):
def __init__(self,myspec):
generic_riscv.__init__(self,myspec)
+class arch_rv64_lp64_musl(generic_riscv):
+ "builder class for rv64_lp64_musl"
+ def __init__(self,myspec):
+ generic_riscv.__init__(self,myspec)
+ self.settings["CHOST"]="riscv64-gentoo-linux-musl"
+
class arch_rv32_ilp32d(generic_riscv):
"builder class for rv32_ilp32d"
def __init__(self,myspec):