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* i386: Only check suffix in instruction mnemonicH.J. Lu2019-11-086-44/+69
* x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich2019-11-082-6/+13
* x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich2019-11-082-43/+53
* x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich2019-11-082-14/+20
* x86: convert SReg from bitfield to enumeratorJan Beulich2019-11-083-9/+18
* x86: introduce operand type "class"Jan Beulich2019-11-082-41/+73
* [gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson2019-11-073-0/+20
* [Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2019-11-076-5/+171
* [binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson2019-11-0711-0/+330
* [Patch][binutils][aarch64] .bfloat16 directive for AArch64 [7/10]Matthew Malcomson2019-11-075-0/+98
* [Patch][binutils][arm] .bfloat16 directive for Arm [6/X]Matthew Malcomson2019-11-075-0/+96
* [Patch][binutils] Generic support for parsing numbers in bfloat16 format [5/X]Matthew Malcomson2019-11-073-29/+63
* [binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2019-11-0718-24/+807
* [binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson2019-11-0710-0/+372
* [gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson2019-11-073-1/+8
* x86: support further AMD Zen2 instructionsJan Beulich2019-11-0710-55/+45
* x86: adjust register names printed for MONITOR/MWAITJan Beulich2019-11-0712-201/+80
* x86: re-arrange process_operands()Jan Beulich2019-11-042-57/+54
* i386; Add .code16gcc fldenv testsH.J. Lu2019-10-313-2/+20
* Add support for context sensitive '.arch_extension' to the ARM assembler.Mihail Ionescu2019-10-316-0/+68
* Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv2019-10-306-44/+86
* x86: add tests to cover defaulting of operand sizes for ambiguous insnsJan Beulich2019-10-308-0/+392
* x86: drop stray WJan Beulich2019-10-302-5/+11
* Re: Optimise away eh_frame advance_loc 0Alan Modra2019-10-292-1/+12
* Add some missing casts to suppress implicit cast warningsJohn David Anglin2019-10-262-5/+12
* Optimise away eh_frame advance_loc 0Alan Modra2019-10-263-4/+28
* PR25125, relaxation chooses wrong branch sizeAlan Modra2019-10-252-4/+13
* qsort: tc-xtensa.c tidyAlan Modra2019-10-162-22/+33
* remove more xmalloc in bfdAlan Modra2019-10-152-6/+12
* Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2019-10-093-0/+19
* S/390: Add support for z15 as CPU name.Andreas Krebbel2019-10-083-4/+5
* Add support for new functionality in the msp430 backend of GCC.Jozef Lawrynowicz2019-10-0717-4/+252
* add missing ChangeLog entry for d241b91073Jan Beulich2019-10-071-0/+13
* x86/Intel: correct MOVSD and CMPSD handlingJan Beulich2019-10-079-12/+233
* Arm: Fix out of range conditional branch (PR/24991)Tamar Christina2019-09-245-7/+38
* [ARM]: Modify assembler to accept floating and signless datatypes for MVE ins...Srinath Parvathaneni2019-09-245-6/+81
* ecoff bfd.h tidyAlan Modra2019-09-233-0/+7
* arm bfd.h tidyAlan Modra2019-09-232-0/+5
* tc-i386.c gcc10 warning fixAlan Modra2019-09-212-2/+6
* bfd macro conversion to inline functions, sectionAlan Modra2019-09-202-1/+5
* x86-64: fix handling of PUSH/POP of segment registerJan Beulich2019-09-204-4/+25
* [gas][news] NEWS (2.33) note new SVE2 and TME instructions for AArch64Matthew Malcomson2019-09-192-0/+10
* bfd_section_* macrosAlan Modra2019-09-1973-370/+358
* bfd_asymbol_* macrosAlan Modra2019-09-182-2/+7
* Re-generate many configure and Makefile.in filesSimon Marchi2019-09-184-22/+14
* RISC-V: Gate opcode tables by enum rather than string.Jim Wilson2019-09-172-7/+26
* Update version to 2.33.50 and regenerate configure scripts.Phil Blundell2019-09-164-18/+36
* Enhance the disassembler so that it will reliably determine whether a reloc a...Nick Clifton2019-09-103-0/+41
* [PATCH][ARM][GAS]: Support to MVE VCTP instruction.Srinath Parvathaneni2019-09-106-0/+177
* Add markers for 2.33 branch to NEWS and ChangeLog files.Phil Blundell2019-09-092-0/+6