Get Gentoo!
gentoo.org sites
gentoo.org Wiki Bugs Forums Packages
Planet Archives Sources
Infra Status
aboutsummaryrefslogtreecommitdiff
path: root/opcodes/i386-opc.tbl
Commit message (Expand)AuthorAgeFilesLines
* x86: re-do "shorthand" handlingJan Beulich2019-10-301-0/+12
* x86: drop stray WJan Beulich2019-10-301-6/+6
* x86/Intel: correct MOVSD and CMPSD handlingJan Beulich2019-10-071-4/+4
* x86-64: fix handling of PUSH/POP of segment registerJan Beulich2019-09-201-2/+4
* x86: drop stray FloatMFJan Beulich2019-08-071-7/+7
* x86: make RegMem an opcode modifierJan Beulich2019-07-161-35/+38
* x86: fold SReg{2,3}Jan Beulich2019-07-161-10/+6
* x86: drop Vec_Imm4Jan Beulich2019-07-011-4/+4
* x86: limit ImmExt abuseJan Beulich2019-07-011-42/+42
* x86: optimize AND/OR with twice the same registerJan Beulich2019-07-011-2/+2
* x86-64: optimize certain commutative VEX-encoded insnsJan Beulich2019-07-011-167/+172
* x86: optimize EVEX packed integer logical instructionsJan Beulich2019-07-011-4/+4
* x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich2019-07-011-0/+8
* x86: drop bogus Disp8MemShift attributesJan Beulich2019-07-011-3/+3
* x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich2019-06-251-1/+1
* x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich2019-06-251-1/+1
* Enable Intel AVX512_VP2INTERSECT insnH.J. Lu2019-06-041-0/+7
* Add support for Intel ENQCMD[S] instructionsH.J. Lu2019-06-041-0/+9
* x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVLH.J. Lu2019-05-281-2/+2
* x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu2019-04-081-22/+7
* x86: Support Intel AVX512 BF16Xuepeng Guo2019-04-051-0/+30
* x86: Optimize EVEX vector load/store instructionsH.J. Lu2019-03-181-6/+6
* Update year range in copyright notice of binutils filesAlan Modra2019-01-011-1/+1
* x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*Jan Beulich2018-11-061-9/+9
* x86: adjust {,E}VEX.W handling outside of 64-bit modeJan Beulich2018-11-061-16/+16
* x86: fix various non-LIG templatesJan Beulich2018-11-061-43/+53
* x86: allow {store} to select alternative {,}PEXTRW encodingJan Beulich2018-11-061-7/+6
* x86: add more VexWIGJan Beulich2018-11-061-143/+143
* x86: XOP VPHADD* / VPHSUB* are VEX.W0Jan Beulich2018-11-061-17/+19
* x86: fold Size{16,32,64} template attributesJan Beulich2018-10-101-0/+4
* x86: Add Intel ENCLV to assembler and disassemblerH.J. Lu2018-10-051-0/+1
* x86: Set EVex=2 on EVEX.128 only vmovd and vmovqH.J. Lu2018-09-171-4/+4
* x86: Set Vex=1 on VEX.128 only vmovd and vmovqH.J. Lu2018-09-171-8/+8
* x86: Replace VexW=3 with VexWIGH.J. Lu2018-09-171-468/+470
* x86: Set VexW=3 on AVX vrsqrtssH.J. Lu2018-09-151-1/+1
* x86: Set Vex=1 on VEX.128 only vmovqH.J. Lu2018-09-151-2/+2
* x86: Support VEX/EVEX WIG encodingH.J. Lu2018-09-141-467/+467
* x86: fold CRC32 templatesJan Beulich2018-09-141-6/+2
* x86: Remove VexW=1 from WIG VEX movq and vmovqH.J. Lu2018-09-131-4/+4
* i386: Update VexW field for VEX instructionsH.J. Lu2018-09-131-18/+18
* x86: drop bogus IgnoreSize from a few further insnsJan Beulich2018-09-131-26/+26
* x86: drop bogus IgnoreSize from AVX512_4* insnsJan Beulich2018-09-131-6/+6
* x86: drop bogus IgnoreSize from AVX512DQ insnsJan Beulich2018-09-131-48/+48
* x86: drop bogus IgnoreSize from AVX512BW insnsJan Beulich2018-09-131-40/+40
* x86: drop bogus IgnoreSize from AVX512VL insnsJan Beulich2018-09-131-13/+13
* x86: drop bogus IgnoreSize from AVX512ER insnsJan Beulich2018-09-131-16/+16
* x86: drop bogus IgnoreSize from AVX512F insnsJan Beulich2018-09-131-371/+371
* x86: drop bogus IgnoreSize from SHA insnsJan Beulich2018-09-131-8/+8
* x86: drop bogus IgnoreSize from XOP and SSE4a insnsJan Beulich2018-09-131-133/+133
* x86: drop bogus IgnoreSize from AVX2 insnsJan Beulich2018-09-131-119/+119