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path:
root
/
opcodes
/
i386-opc.tbl
Commit message (
Expand
)
Author
Age
Files
Lines
*
x86: re-do "shorthand" handling
Jan Beulich
2019-10-30
1
-0
/
+12
*
x86: drop stray W
Jan Beulich
2019-10-30
1
-6
/
+6
*
x86/Intel: correct MOVSD and CMPSD handling
Jan Beulich
2019-10-07
1
-4
/
+4
*
x86-64: fix handling of PUSH/POP of segment register
Jan Beulich
2019-09-20
1
-2
/
+4
*
x86: drop stray FloatMF
Jan Beulich
2019-08-07
1
-7
/
+7
*
x86: make RegMem an opcode modifier
Jan Beulich
2019-07-16
1
-35
/
+38
*
x86: fold SReg{2,3}
Jan Beulich
2019-07-16
1
-10
/
+6
*
x86: drop Vec_Imm4
Jan Beulich
2019-07-01
1
-4
/
+4
*
x86: limit ImmExt abuse
Jan Beulich
2019-07-01
1
-42
/
+42
*
x86: optimize AND/OR with twice the same register
Jan Beulich
2019-07-01
1
-2
/
+2
*
x86-64: optimize certain commutative VEX-encoded insns
Jan Beulich
2019-07-01
1
-167
/
+172
*
x86: optimize EVEX packed integer logical instructions
Jan Beulich
2019-07-01
1
-4
/
+4
*
x86: add missing pseudo ops for VPCLMULQDQ ISA extension
Jan Beulich
2019-07-01
1
-0
/
+8
*
x86: drop bogus Disp8MemShift attributes
Jan Beulich
2019-07-01
1
-3
/
+3
*
x86: fix (dis)assembly of certain SSE2 insns in 16-bit mode
Jan Beulich
2019-06-25
1
-1
/
+1
*
x86-64: also optimize ANDQ with immediate fitting in 7 bits
Jan Beulich
2019-06-25
1
-1
/
+1
*
Enable Intel AVX512_VP2INTERSECT insn
H.J. Lu
2019-06-04
1
-0
/
+7
*
Add support for Intel ENQCMD[S] instructions
H.J. Lu
2019-06-04
1
-0
/
+9
*
x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL
H.J. Lu
2019-05-28
1
-2
/
+2
*
x86: Consolidate AVX512 BF16 entries in i386-opc.tbl
H.J. Lu
2019-04-08
1
-22
/
+7
*
x86: Support Intel AVX512 BF16
Xuepeng Guo
2019-04-05
1
-0
/
+30
*
x86: Optimize EVEX vector load/store instructions
H.J. Lu
2019-03-18
1
-6
/
+6
*
Update year range in copyright notice of binutils files
Alan Modra
2019-01-01
1
-1
/
+1
*
x86: adjust {,E}VEX.W handling for PEXTR* / PINSR*
Jan Beulich
2018-11-06
1
-9
/
+9
*
x86: adjust {,E}VEX.W handling outside of 64-bit mode
Jan Beulich
2018-11-06
1
-16
/
+16
*
x86: fix various non-LIG templates
Jan Beulich
2018-11-06
1
-43
/
+53
*
x86: allow {store} to select alternative {,}PEXTRW encoding
Jan Beulich
2018-11-06
1
-7
/
+6
*
x86: add more VexWIG
Jan Beulich
2018-11-06
1
-143
/
+143
*
x86: XOP VPHADD* / VPHSUB* are VEX.W0
Jan Beulich
2018-11-06
1
-17
/
+19
*
x86: fold Size{16,32,64} template attributes
Jan Beulich
2018-10-10
1
-0
/
+4
*
x86: Add Intel ENCLV to assembler and disassembler
H.J. Lu
2018-10-05
1
-0
/
+1
*
x86: Set EVex=2 on EVEX.128 only vmovd and vmovq
H.J. Lu
2018-09-17
1
-4
/
+4
*
x86: Set Vex=1 on VEX.128 only vmovd and vmovq
H.J. Lu
2018-09-17
1
-8
/
+8
*
x86: Replace VexW=3 with VexWIG
H.J. Lu
2018-09-17
1
-468
/
+470
*
x86: Set VexW=3 on AVX vrsqrtss
H.J. Lu
2018-09-15
1
-1
/
+1
*
x86: Set Vex=1 on VEX.128 only vmovq
H.J. Lu
2018-09-15
1
-2
/
+2
*
x86: Support VEX/EVEX WIG encoding
H.J. Lu
2018-09-14
1
-467
/
+467
*
x86: fold CRC32 templates
Jan Beulich
2018-09-14
1
-6
/
+2
*
x86: Remove VexW=1 from WIG VEX movq and vmovq
H.J. Lu
2018-09-13
1
-4
/
+4
*
i386: Update VexW field for VEX instructions
H.J. Lu
2018-09-13
1
-18
/
+18
*
x86: drop bogus IgnoreSize from a few further insns
Jan Beulich
2018-09-13
1
-26
/
+26
*
x86: drop bogus IgnoreSize from AVX512_4* insns
Jan Beulich
2018-09-13
1
-6
/
+6
*
x86: drop bogus IgnoreSize from AVX512DQ insns
Jan Beulich
2018-09-13
1
-48
/
+48
*
x86: drop bogus IgnoreSize from AVX512BW insns
Jan Beulich
2018-09-13
1
-40
/
+40
*
x86: drop bogus IgnoreSize from AVX512VL insns
Jan Beulich
2018-09-13
1
-13
/
+13
*
x86: drop bogus IgnoreSize from AVX512ER insns
Jan Beulich
2018-09-13
1
-16
/
+16
*
x86: drop bogus IgnoreSize from AVX512F insns
Jan Beulich
2018-09-13
1
-371
/
+371
*
x86: drop bogus IgnoreSize from SHA insns
Jan Beulich
2018-09-13
1
-8
/
+8
*
x86: drop bogus IgnoreSize from XOP and SSE4a insns
Jan Beulich
2018-09-13
1
-133
/
+133
*
x86: drop bogus IgnoreSize from AVX2 insns
Jan Beulich
2018-09-13
1
-119
/
+119
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