diff options
Diffstat (limited to 'trunk/2.6.22/20052_xen3-x86-fam10-l3cache.patch1')
| -rw-r--r-- | trunk/2.6.22/20052_xen3-x86-fam10-l3cache.patch1 | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/trunk/2.6.22/20052_xen3-x86-fam10-l3cache.patch1 b/trunk/2.6.22/20052_xen3-x86-fam10-l3cache.patch1 new file mode 100644 index 0000000..b54659c --- /dev/null +++ b/trunk/2.6.22/20052_xen3-x86-fam10-l3cache.patch1 @@ -0,0 +1,28 @@ +Subject: i386: Add L3 cache support to AMD CPUID4 emulation + +With that an L3 cache is correctly reported in the cache information in /sys + +With fixes from Andreas Herrmann and Dean Gaudet and Joachim Deguara + +Signed-off-by: Andi Kleen <ak@suse.de> + +Automatically created from "patches.arch/x86-fam10-l3cache" by xen-port-patches.py + +Index: head-2007-08-22/arch/x86_64/kernel/setup-xen.c +=================================================================== +--- head-2007-08-22.orig/arch/x86_64/kernel/setup-xen.c 2007-08-22 09:54:14.000000000 +0200 ++++ head-2007-08-22/arch/x86_64/kernel/setup-xen.c 2007-08-22 09:56:51.000000000 +0200 +@@ -856,8 +856,11 @@ static void __cpuinit init_amd(struct cp + if (c->extended_cpuid_level >= 0x80000008) + amd_detect_cmp(c); + +- /* Fix cpuid4 emulation for more */ +- num_cache_leaves = 3; ++ if (c->extended_cpuid_level >= 0x80000006 && ++ (cpuid_edx(0x80000006) & 0xf000)) ++ num_cache_leaves = 4; ++ else ++ num_cache_leaves = 3; + + /* RDTSC can be speculated around */ + clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability); |