backport upstream fix for sse2 code generation

Package-Manager: portage-2.0.51.22-r1

2 files changed, 143 insertions, 4 deletions

diff --git a/sys-devel/gcc/files/3.4.4/gcc-3.4.4-fix-sse2-pinsrw.patch b/sys-devel/gcc/files/3.4.4/gcc-3.4.4-fix-sse2-pinsrw.patch
new file mode 100644
index 000000000000..721ff7df9a93
--- /dev/null
+++ b/sys-devel/gcc/files/3.4.4/gcc-3.4.4-fix-sse2-pinsrw.patch
@@ -0,0 +1,140 @@
+Back ported from mainline to gcc-3.4
+
+http://gcc.gnu.org/bugzilla/show_bug.cgi?id=14631
+http://gcc.gnu.org/ml/gcc-patches/2004-09/msg01949.html
+
+2005-01-03  Richard Henderson  <rth@redhat.com>
+	    Uros Bizjak  <uros@kss-loka.si>
+
+	PR target/14631
+	* config/i386/i386.c (ix86_expand_builtin): [IX86_BUILTIN_PINSRW,
+	IX86_BUILTIN_PINSRW128]: Fix wrong selector range in error message.
+	* config/i386/i386.md (mmx_pinsrw, sse2_pinsrw): Fix selector
+	handling.
+	(*mmx_pinsrw, *sse2_pinsrw): New patterns.
+	* config/i386/i386/predicates.md (const_pow2_1_to_8_operand,
+	const_pow2_1_to_128_operand): New predicates.
+
+--- gcc/gcc/config/i386/i386.c
++++ gcc/gcc/config/i386/i386.c
+@@ -3820,6 +3820,21 @@
+   return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 256);
+ }
+ 
++/* Match exactly one bit in 4-bit mask. */
++int
++const_pow2_1_to_8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
++{
++  unsigned int log = exact_log2 (INTVAL (op));
++  return log <= 3;
++}
++
++/* Match exactly one bit in 8-bit mask. */
++int
++const_pow2_1_to_128_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
++{
++  unsigned int log = exact_log2 (INTVAL (op));
++  return log <= 7;
++}
+ 
+ /* True if this is a constant appropriate for an increment or decrement.  */
+ 
+@@ -13437,7 +13437,7 @@
+       if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
+ 	{
+ 	  error ("selector must be an integer constant in the range 0..%i",
+-		  fcode == IX86_BUILTIN_PINSRW ? 15:255);
++		  fcode == IX86_BUILTIN_PINSRW ? 3:7);
+ 	  return const0_rtx;
+ 	}
+       if (target == 0
+--- gcc/gcc/config/i386/i386.md
++++ gcc/gcc/config/i386/i386.md
+@@ -21446,14 +21446,31 @@
+ 
+ ;; MMX insert/extract/shuffle
+ 
+-(define_insn "mmx_pinsrw"
++(define_expand "mmx_pinsrw"
++  [(set (match_operand:V4HI 0 "register_operand" "")
++        (vec_merge:V4HI
++	  (match_operand:V4HI 1 "register_operand" "")
++          (vec_duplicate:V4HI
++            (match_operand:SI 2 "nonimmediate_operand" ""))
++          (match_operand:SI 3 "const_0_to_3_operand" "")))]
++  "TARGET_SSE || TARGET_3DNOW_A"
++{
++  operands[2] = gen_lowpart (HImode, operands[2]);
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++})
++
++(define_insn "*mmx_pinsrw"
+   [(set (match_operand:V4HI 0 "register_operand" "=y")
+-        (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
+-			(vec_duplicate:V4HI
+-			 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
+-			(match_operand:SI 3 "const_0_to_15_operand" "N")))]
++        (vec_merge:V4HI
++	  (match_operand:V4HI 1 "register_operand" "0")
++          (vec_duplicate:V4HI
++            (match_operand:HI 2 "nonimmediate_operand" "rm"))
++          (match_operand:SI 3 "const_pow2_1_to_8_operand" "N")))]
+   "TARGET_SSE || TARGET_3DNOW_A"
+-  "pinsrw\t{%3, %2, %0|%0, %2, %3}"
++{
++  operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
++  return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
++}
+   [(set_attr "type" "mmxcvt")
+    (set_attr "mode" "DI")])
+ 
+@@ -23141,15 +23158,31 @@
+ 
+ ;; MMX insert/extract/shuffle
+ 
+-(define_insn "sse2_pinsrw"
++(define_expand "sse2_pinsrw"
++  [(set (match_operand:V8HI 0 "register_operand" "")
++        (vec_merge:V8HI
++	  (match_operand:V8HI 1 "register_operand" "")
++          (vec_duplicate:V8HI
++            (match_operand:SI 2 "nonimmediate_operand" ""))
++          (match_operand:SI 3 "const_0_to_7_operand" "")))]
++  "TARGET_SSE2"
++{
++  operands[2] = gen_lowpart (HImode, operands[2]);
++  operands[3] = GEN_INT (1 << INTVAL (operands[3]));
++})
++
++(define_insn "*sse2_pinsrw"
+   [(set (match_operand:V8HI 0 "register_operand" "=x")
+-        (vec_merge:V8HI (match_operand:V8HI 1 "register_operand" "0")
+-			(vec_duplicate:V8HI
+-			 (truncate:HI
+-			   (match_operand:SI 2 "nonimmediate_operand" "rm")))
+-			(match_operand:SI 3 "const_0_to_255_operand" "N")))]
++        (vec_merge:V8HI
++	  (match_operand:V8HI 1 "register_operand" "0")
++          (vec_duplicate:V8HI
++            (match_operand:HI 2 "nonimmediate_operand" "rm"))
++          (match_operand:SI 3 "const_pow2_1_to_128_operand" "N")))]
+   "TARGET_SSE2"
+-  "pinsrw\t{%3, %2, %0|%0, %2, %3}"
++{
++  operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
++  return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
++}
+   [(set_attr "type" "ssecvt")
+    (set_attr "mode" "TI")])
+ 
+--- gcc/gcc/config/i386/i386.h
++++ gcc/gcc/config/i386/i386.h
+@@ -2944,6 +2944,8 @@
+   {"const_0_to_7_operand", {CONST_INT}},				\
+   {"const_0_to_15_operand", {CONST_INT}},				\
+   {"const_0_to_255_operand", {CONST_INT}},				\
++  {"const_pow2_1_to_8_operand", {CONST_INT}}, \
++  {"const_pow2_1_to_128_operand", {CONST_INT}}, \
+   {"incdec_operand", {CONST_INT}},					\
+   {"mmx_reg_operand", {REG}},						\
+   {"reg_no_sp_operand", {SUBREG, REG}},					\
diff --git a/sys-devel/gcc/gcc-3.4.4.ebuild b/sys-devel/gcc/gcc-3.4.4.ebuild
index 7660df415ee0..355692a4ff18 100644
--- a/sys-devel/gcc/gcc-3.4.4.ebuild
+++ b/sys-devel/gcc/gcc-3.4.4.ebuild
@@ -1,6 +1,6 @@
 # Copyright 1999-2005 Gentoo Foundation
 # Distributed under the terms of the GNU General Public License v2
-# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc/gcc-3.4.4.ebuild,v 1.2 2005/05/25 03:29:09 vapier Exp $
+# $Header: /var/cvsroot/gentoo-x86/sys-devel/gcc/gcc-3.4.4.ebuild,v 1.3 2005/05/25 22:34:17 vapier Exp $
 
 MAN_VER=""
 PATCH_VER="1.0"
@@ -90,9 +90,8 @@ src_unpack() {
 		#epatch ${FILESDIR}/3.4.3/libffi-nogcj-lib-path-fix.patch
 	fi
 
-	# hack around some ugly 32bit sse2 wrong-code bugs
-	epatch "${FILESDIR}"/3.4.2/gcc34-m32-no-sse2.patch
-	epatch "${FILESDIR}"/3.4.2/gcc34-fix-sse2_pinsrw.patch
+	# Grab fixes for remaining SSE wrong-code bugs
+	epatch "${FILESDIR}"/3.4.4/gcc-3.4.4-fix-sse2-pinsrw.patch
 
 	# Fix cross-compiling
 	epatch "${FILESDIR}"/3.4.4/gcc-3.4.4-cross-compile.patch