sci-electronics/circt: new package, add 1.14.0

Signed-off-by: Huang Rui <vowstar@gmail.com>

3 files changed, 136 insertions, 0 deletions

diff --git a/sci-electronics/circt/Manifest b/sci-electronics/circt/Manifest
new file mode 100644
index 000000000..4fd0d394c
--- /dev/null
+++ b/sci-electronics/circt/Manifest
@@ -0,0 +1,2 @@
+DIST circt-1.14.0.tar.gz 2152570 BLAKE2B 3901c0d146a4410cc2ee5a0556ce54decea4fb1998b83a2999ec97493efcdefbb2bb0c33b5ee127c9627568bdd92669bf1c064930abf6954aa33cbb382fea006 SHA512 1d2b2696c7ce42cf90a9209f2b0d04862681645cfe733e0dd2f6c48754a9fa035f2d5033b2c0278841edaaee9a72802a00226f210a032e81b79d4d3df5bcf7cf
+DIST llvm-project-fe0f72d5c55a9b95c5564089e946e8f08112e995.tar.gz 166019098 BLAKE2B c3613d5465522249597fe8a882cd4cdd2f8b4030a9fee73c47643f0e64ea0b97a212f9e4637e5a096e30e679460dac039b0c244daf4b0bd04c4da42efb4744d0 SHA512 bc71f42c8af87559fbc384a6cf473b5bdb42a04e698e7e44c94d9ea27f763d7f0bd4dea63e0eef9d29cdfb2ad203b14eeb6431bba336583cfb0ce19f12a40a72
diff --git a/sci-electronics/circt/circt-1.14.0.ebuild b/sci-electronics/circt/circt-1.14.0.ebuild
new file mode 100644
index 000000000..14b7a0b36
--- /dev/null
+++ b/sci-electronics/circt/circt-1.14.0.ebuild
@@ -0,0 +1,116 @@
+# Copyright 1999-2022 Gentoo Authors
+# Distributed under the terms of the GNU General Public License v2
+
+EAPI="8"
+
+MY_PV="$(ver_cut 1)/$(ver_cut 2)/$(ver_cut 3)"
+MY_LLVM_PV="fe0f72d5c55a9b95c5564089e946e8f08112e995"
+CMAKE_BUILD_TYPE="Release"
+CMAKE_MAKEFILE_GENERATOR="ninja"
+PYTHON_COMPAT=( python3_{8..11} )
+inherit cmake python-r1
+
+DESCRIPTION="The fast free Verilog/SystemVerilog simulator"
+HOMEPAGE="
+	https://circt.llvm.org
+	https://github.com/llvm/circt
+"
+
+if [[ "${PV}" == "9999" ]] ; then
+	inherit git-r3
+	EGIT_REPO_URI="https://github.com/llvm/${PN}.git"
+	EGIT_SUBMODULES=( '*' )
+else
+	SRC_URI="
+		https://github.com/llvm/circt/archive/refs/tags/sifive/${MY_PV}.tar.gz -> ${P}.tar.gz
+		https://github.com/llvm/llvm-project/archive/${MY_LLVM_PV}.tar.gz -> llvm-project-${MY_LLVM_PV}.tar.gz
+	"
+	KEYWORDS="~amd64 ~arm64 ~riscv ~x86"
+	S_CIRCT="${WORKDIR}/${PN}-sifive-$(ver_cut 1)-$(ver_cut 2)-$(ver_cut 3)"
+	S_LLVM="${WORKDIR}/llvm-project-${MY_LLVM_PV}"
+	S="${S_LLVM}/llvm"
+fi
+
+LICENSE="Apache-2.0-with-LLVM-exceptions UoI-NCSA BSD public-domain rc"
+SLOT="0"
+IUSE="test"
+REQUIRED_USE=" ${PYTHON_REQUIRED_USE} "
+
+RESTRICT="!test? ( test )"
+
+RDEPEND="
+	${PYTHON_DEPS}
+	test? (
+		dev-python/psutil[${PYTHON_USEDEP}]
+		sci-electronics/verilator
+	)
+	sys-libs/ncurses:0=
+"
+
+DEPEND="
+	${RDEPEND}
+"
+
+BDEPEND="
+	dev-util/ninja
+	virtual/pkgconfig
+"
+
+DOCS=(
+	"${S_LLVM}/llvm/llvm-LICENSE.TXT"
+	"${S_LLVM}/mlir/mlir-LICENSE.TXT"
+	"${S_CIRCT}/circt-LICENSE"
+)
+
+src_configure() {
+	python_setup
+
+	local mycmakeargs=(
+		-D Python3_EXECUTABLE="${PYTHON}" \
+		-D CMAKE_INSTALL_PREFIX=/usr \
+		-D LLVM_BINUTILS_INCDIR=/usr/include \
+		-D LLVM_ENABLE_PROJECTS=mlir \
+		-D BUILD_SHARED_LIBS=OFF \
+		-D LLVM_STATIC_LINK_CXX_STDLIB=ON \
+		-D LLVM_ENABLE_ASSERTIONS=ON \
+		-D LLVM_BUILD_EXAMPLES=OFF \
+		-D LLVM_ENABLE_BINDINGS=OFF \
+		-D LLVM_ENABLE_OCAMLDOC=OFF \
+		-D LLVM_OPTIMIZED_TABLEGEN=ON \
+		-D LLVM_EXTERNAL_PROJECTS=circt \
+		-D LLVM_EXTERNAL_CIRCT_SOURCE_DIR="${S_CIRCT}" \
+		-D LLVM_BUILD_TOOLS=ON
+	)
+	cmake_src_configure
+}
+
+src_test() {
+	pushd "${BUILD_DIR}" || die
+	eninja check-mlir
+	eninja check-circt
+	eninja check-circt-integration
+	popd || die
+}
+
+src_install() {
+	mv "${S_LLVM}/llvm/LICENSE.TXT" "${S_LLVM}/llvm/llvm-LICENSE.TXT" || die
+	mv "${S_LLVM}/mlir/LICENSE.TXT" "${S_LLVM}/mlir/mlir-LICENSE.TXT" || die
+	mv "${S_CIRCT}/LICENSE" "${S_CIRCT}/circt-LICENSE" || die
+	einstalldocs
+	exeinto /usr/bin
+	doexe "${BUILD_DIR}"/bin/circt-capi-ir-test
+	doexe "${BUILD_DIR}"/bin/circt-lsp-server
+	doexe "${BUILD_DIR}"/bin/circt-opt
+	doexe "${BUILD_DIR}"/bin/circt-reduce
+	doexe "${BUILD_DIR}"/bin/circt-rtl-sim.py
+	doexe "${BUILD_DIR}"/bin/circt-translate
+	doexe "${BUILD_DIR}"/bin/esi_cosim.py
+	doexe "${BUILD_DIR}"/bin/esi-cosim-runner.py
+	doexe "${BUILD_DIR}"/bin/esi-tester
+	doexe "${BUILD_DIR}"/bin/firtool
+	doexe "${BUILD_DIR}"/bin/handshake-runner
+	doexe "${BUILD_DIR}"/bin/llhd-sim
+	doexe "${BUILD_DIR}"/bin/py-split-input-file.py
+	# llhd-sim not static linked
+	dolib.so "${BUILD_DIR}"/lib/libcirct-llhd-signals-runtime-wrappers.so
+}
diff --git a/sci-electronics/circt/metadata.xml b/sci-electronics/circt/metadata.xml
new file mode 100644
index 000000000..ce85e6abd
--- /dev/null
+++ b/sci-electronics/circt/metadata.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE pkgmetadata SYSTEM "https://www.gentoo.org/dtd/metadata.dtd">
+<pkgmetadata>
+	<maintainer type="person">
+		<email>vowstar@gmail.com</email>
+		<name>Huang Rui</name>
+	</maintainer>
+	<upstream>
+		<remote-id type="github">verilator/verilator</remote-id>
+	</upstream>
+	<longdescription lang="en">
+	Verilator, the fastest free Verilog HDL simulator.
+	Accepts synthesizable Verilog or SystemVerilog
+	Performs lint code-quality checks
+	Compiles into multithreaded C++, SystemC, or (soon) C++-under-Python
+	Creates XML to front-end your own tools
+	</longdescription>
+</pkgmetadata>