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| author |   Yuhang Zeng <unlsycn@unlsycn.com> | 2024-06-13 00:29:47 +0800 |
|---|---|---|
| committer | Yuhang Zeng <unlsycn@unlsycn.com> | 2024-06-13 00:33:10 +0800 |
| commit | fe47557fbada13a64eacab72846fd49a0530959f (patch) | |
| tree | f0f987f68338bd99999f1468bc18b14feae16828 /sci-electronics | |
| parent | sci-electronics/circt: add 1.76.0 (diff) | |
| download | guru-fe47557fbada13a64eacab72846fd49a0530959f.tar.gz guru-fe47557fbada13a64eacab72846fd49a0530959f.tar.bz2 guru-fe47557fbada13a64eacab72846fd49a0530959f.zip | |
sci-electronics/circt: enable py3.12 and disable py3.10
Signed-off-by: Yuhang Zeng <unlsycn@unlsycn.com>
Diffstat (limited to 'sci-electronics')
| -rw-r--r-- | sci-electronics/circt/circt-1.14.0.ebuild | 2 | ||||
| -rw-r--r-- | sci-electronics/circt/circt-1.37.0.ebuild | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/sci-electronics/circt/circt-1.14.0.ebuild b/sci-electronics/circt/circt-1.14.0.ebuild index 181b5b44f..42854ef96 100644 --- a/sci-electronics/circt/circt-1.14.0.ebuild +++ b/sci-electronics/circt/circt-1.14.0.ebuild @@ -6,7 +6,7 @@ EAPI="8" MY_PV="${PV//./\/}" MY_LLVM_PV="fe0f72d5c55a9b95c5564089e946e8f08112e995" CMAKE_BUILD_TYPE="Release" -PYTHON_COMPAT=( python3_{10..11} ) +PYTHON_COMPAT=( python3_{11..12} ) inherit cmake python-r1 DESCRIPTION="The fast free Verilog/SystemVerilog simulator" diff --git a/sci-electronics/circt/circt-1.37.0.ebuild b/sci-electronics/circt/circt-1.37.0.ebuild index ce9f7c46b..0b1a877e5 100644 --- a/sci-electronics/circt/circt-1.37.0.ebuild +++ b/sci-electronics/circt/circt-1.37.0.ebuild @@ -6,7 +6,7 @@ EAPI="8" MY_PV="${PV//./\/}" MY_LLVM_PV="d978730d8e2c10c76867b83bec2f1143d895ee7d" CMAKE_BUILD_TYPE="Release" -PYTHON_COMPAT=( python3_{10..11} ) +PYTHON_COMPAT=( python3_{11..12} ) inherit cmake python-r1 DESCRIPTION="The fast free Verilog/SystemVerilog simulator" |